Computer Architecture Probe

a graphical simulator that illustrates the operation from multiple layers

Best Poster Presentation for Computer Science, Undergraduate Research Symposium

Computer Science Capstone, NYU Shanghai

in collaboration with Yuxia Yao

May 2018

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In the course of Computer Architecture, we learned how a modern computer works through multiple layers of interface, connecting both hardware and software. In order to study the layers that usually work 'behind the scene' of real computers, students turn to graphical simulators to observe the interaction between components.

Most simulators focus on one particular layer. While such tools help grasp the theoretical concepts of particular layers, they fail in helping students master the relation and translation between two layers of interface.

Hence, there is a need for a graphical simulator that illustrates the operation of all layers during program execution, starting from a high-level programming language to its most elementary components (transistors, resistors, capacitors).

The project Computer Architecture Probe (CAP) is a web-based graphical simulator of all layers of the computer architecture based on MIPS. Given a user-input code in C language, CAP translates it into Assembly Instruction Codes (AIC) using Compiler Explorer API. Then it simulates and renders the output in microarchitecture, gate, intermediate and transistor layers.

Users can execute the code step by step and zoom in or out to see the simulation in any layer at anytime.

1-mips.png

The 1st layer is an overview of all microarchitecture components in a single-cycle MIPS processor. Datapaths are highlighted only if their data count toward the calculation. In this example, it is executing addiu $sp, $sp, -24.

2-alu.png

The 2nd layer shows ALU component in gate level. It takes inputs A and B and generates the result based on a 3-digit ALU Control Code. Datapaths are highlighted only if their data count toward the calculation.

3-gate.png

The 3rd layer gives a diagram of a 4-bit additon block in gate level. The path is highlighted in cyan when its value is 1.

4-transistor.png

The 4th level reveals a conventional design of a full adder in transistor level. A full adder takes three binary input a, b and a carry-in and calculates the sum and carry-out. The green lines represent the current flow. In this specific example, this full adder sums a=0 and b=1, with a carry-in=0.